News

• 4/2023: I will organize a tutorial on Reinforcement Learning for Computer Architecture and Systems Research (RL4CAS) at ISCA 2023. See you in Orlando. Find more info at https://rl4cas.github.io/

• 1/2023: Our paper “MACTA: A Multi-agent Reinforcement Learning Approach for Cache Timing Attacks and Detection” is accepted to ICLR 2023! This is the first paper to develop multi-agent reinforcement learning framework for hardwarwe security problems.

• 10/2022: I will be serving as on the Program Committee (PC) for ASPLOS 2023 and the External Review Committee (ERC) for ISCA 2023.

• 10/2022: Our paper “AutoCAT: Reinforcement Learning for Automated Exploration of Cache Timing-Channel Attacks” is accepted to IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2023! This is the first paper to apply reinforcement learning in hardwarwe security problems.

• 11/2021: Our paper “SecNDP: Secure Near-Data Processing with Untrusted Memory” is accepted to IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2022!

• 04/2021: Our paper “Leaking Information Through Cache LRU States” is selected as the Featured Paper in the April 2021 issue of IEEE Transactions on Computers (TC)!

• 01/2021: Our paper “Leaking Information Through Cache LRU States” is selected as an Honorable Mention of IEEE Micro Top Picks 2021!

Research

Research Overview

- Why security and privacy?

We are living in an increasingly connected world where an unprecedented amount of data are being collected, transferred, and processed across tens of billions of connected devices and systems daily, including private user information or company intellectual properties (IPs). In addition to the pursuit of better performance and lower energy, guaranteeing security and privacy is now considered a first-class citizen in architecting and designing future computing systems.

- Why hardware security?

Foundation of security: Hardware is the bottom layer of the computation stack. Hardware vulnerabilities will compromise the whole system and can hardly be mitigated by software efficiently.
Efficient security solution: Hardware-software co-design for security can yield efficient solutions.
Physical features for security: Hardware is the interface between software and the physical world. The physical and analog features of hardware can be leveraged for security.

- How do we pursue hardware security?

We conduct research in the intersection of computer architecture, circuits, cryptography, formal methods, and machine learning. Our goal is to deliver efficient hardware designs with built-in security.

Research Projects

- Secure Heterogeneous Architectures

It is a trend to include several different computing modules, such as GPU, FPGA, ASIC accelerators, memory, etc., to a computing platform for high-performance computing. The heterogeneous architectures face new security challenges to protect data across different modules. New designs are needed to protect data end-to-end.

- Side and Covert Channel Attacks and Mitigations in Processors

Nowadays, hardware is usually reused for different applications or users. For example, many applications are running on one device, multiple talents may share the same server on the cloud, etc. Sharing of hardware leads to the potential side and covert-channel attacks that lead to information leakage. It is a challenge to understand how these attacks happen and how to mitigate them.

- Device Authentication and Software Protection Leveraging Hardware Features

Hardware has physical and analog features that can be leveraged for security purpose. In our DRAM PUFs project, we leverage the DRAM retention error for device authentication, fingerprinting, key storage, and software protection.

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Publications

Google Scholar · dblp CS Bibliography · ResearchGate

Peer-reviewed Conference Publications

• Sanjay Kariyappa, Chuan Guo, Kiwan Maeng, Wenjie Xiong, G. Edward Suh, Moinuddin K Qureshi, Hsien-Hsin S. Lee
  "Cocktail Party Attack: Breaking Aggregation-Based Privacy in Federated Learning using Independent Component Analysis"
  To be appear in Proceedings of The International Conference on Machine Learning (ICML), 2023.
  [ arXiv ]

• Jiaxun Cui, Xiaomeng Yang^†, Mulong Luo^†, Geunbae Lee^†, Peter Stone, Hsien-Hsin S. Lee, Benjamin Lee, Edward Suh, Wenjie Xiong^{^}, Yuandong Tian^{^}
  "MACTA: A Multi-agent Reinforcement Learning Approach for Cache Timing Attacks and Detection"
  in Proceedings of the 11th International Conference on Learning Representations (ICLR), 2023.
  ^†Equal Second-author Contribution, ^{^}Equal Supervising
  [ PDF ] [ CODE ]

• Mulong Luo^†, Wenjie Xiong^†, John Lee, Yueying Li, Xiaomeng Yang, Yuandong Tian, Amy Zhang, Hsien-Hsin Sean Lee, and G. Edward Suh.
  "AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks"
  in Proceedings of the 29th IEEE International Symposium on High Performance Computer Architecture (HPCA), 2023.
  ^† The authors contributed equally.
  [ PDF ] [ arXiv ] [ CODE ]

• Yuan Liang, Xing Gao, Kun Sun, Wenjie Xiong, and Haining Wang, "An Investigation on Data Center Cooling Systems Using FPGA-based Temperature Side Channels" in Proceedings of the 41st International Symposium on Reliable Distributed Systems (SRDS), Sep 2022.
  [ PDF ]

• Yongqin Wang, G. Edward Suh, Wenjie Xiong, Benjamin Lefaudeux, Brian Knott, Murali Annavaram, Hsien-Hsin S. Lee,
  “Characterization of MPC-based Private Inferences for Transformer-based Models”,
  in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), May 2022.
  [ PDF ]

• Wenjie Xiong^†, Liu Ke^†, Dimitrije Jankov, Michael Kounavis, Xiaochen Wang, Eric Northup, Jie Amy Yang, Bilge Acun, Carole-Jean Wu, Ping Tak Peter Tang, G. Edward Suh, Xuan Zhang, and Hsien-Hsin S. Lee,
  “SecNDP: Secure Near-Data Processing with Untrusted Memory”,
  in Proceedings of the 28th IEEE International Symposium on High Performance Computer Architecture (HPCA), April 2022.
  [ PDF ][ SLIDES ][ ePrint (with full proof) ]

• Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong, and Jakub Szefer,
  "Cloud FPGA Cartography using PCIe Contention",
  in Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2021.
  [ PDF ]

• Shuwen Deng, Wenjie Xiong, and Jakub Szefer,
  "A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks",
  in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2020.
  [ PDF ]

• Shanquan Tian, Wenjie Xiong, Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer,
  "Fingerprinting Cloud FPGA Infrastructures",
  in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), 2020.
  [ PDF ]

• Wenjie Xiong, and Jakub Szefer,
  "Leaking Information Through Cache LRU States",
  in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), February 2020.
  (IEEE Micro Top Picks 2021 Honorable Mention) [ PDF ]
  

• Shuai Chen, Wenjie Xiong, Yehan Xu, Bing Li, and Jakub Szefer,
  "Thermal Covert Channels Leveraging Package-On-Package DRAM",
  in Proceedings of the International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), August 2019.
  [ PDF ] 
  

• Shuwen Deng, Wenjie Xiong, and Jakub Szefer,
  "Secure TLBs",
  in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019.
  (Top Picks in Hardware and Embedded Security 2021)
  [ PDF ] 
  

• Wenjie Xiong, André Schaller, Stefan Katzenbeisser, and Jakub Szefer,
  "Dynamic Physically Unclonable Functions",
  in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), May 2019.
  [ PDF ] 
  

• Wenjie Xiong, Nikolaos Athanasios Anagnostopoulos, André Schaller, Stefan Katzenbeisser, and Jakub Szefer,
  "Spying on Temperature using DRAM",
  in Proceedings of the Design, Automation, and Test in Europe (DATE), March 2019.
  [ PDF ] [ CODE ]
  

• André Schaller, Wenjie Xiong, Muhammad Umair Saleem, Nikolaos A. Anagnostopoulos, Stefan Katzenbeisser, and Jakub Szefer,
  "Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security"
  in Proceedings of the International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.
  (Best Student Paper Finalist)
  [ PDF ] [ CODE ]
  

• Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer,
  "Run-time Accessible DRAM PUFs in Commodity Devices"
  in Proceedings of the Conference on Cryptographic Hardware and Embedded Systems (CHES), August 2016.
  (Top Picks in Hardware and Embedded Security 2019)
  [ PDF ] [ CODE ]
  

Peer-reviewed Journal Publications

• Florian Frank^†, Wenjie Xiong^†, Nikolaos Athanasios Anagnostopoulos, André Schaller, Tolga Arul, Farinaz Koushanfar, Stefan Katzenbeisser, Ulrich Rührmair, and Jakub Szefer,
  "Abusing Commodity DRAMs in IoT Devices to Remotely Spy on Temperature",
  in IEEE Transactions on Information Forensics and Security, 2023.
  ^† The authors contributed equally.
  [ early access ] 

• Ferhat Erata, Shuwen Deng, Faisal Zaghloul, Wenjie Xiong, Onur Demir, and Jakub Szefer,
  "Survey of Approaches and Techniques for Security Verification of Computer Systems",
  in Journal on Emerging Technologies in Computing Systems, vol. 19, no. 1, Article 6 (January 2023).
  [ ePrint ] 

• Shuwen Deng, Nikolay Matyunin, Wenjie Xiong, Stefan Katzenbeisser, and Jakub Szefer,
  "Evaluation of Cache Attacks on Arm Processors and Secure Caches",
  in IEEE Transactions on Computers (TC), November 2021.
  [ PDF ]

• Shuwen Deng, Wenjie Xiong, and Jakub Szefer,
  "Secure TLBs",
  in Top Picks in Hardware and Embedded Security, November 2021.
  

• Wenjie Xiong, and Jakub Szefer,
  "Survey of Transient Execution Attacks and their Mitigations",
  in ACM Computing Surveys (CSUR), vol. 54, no. 3, Article 54, May 2021.
  [ PDF ]

• Shuwen Deng, Wenjie Xiong, and Jakub Szefer,
  "Understanding Insecurity of Processor Caches due to Cache Timing-Based Vulnerabilities",
  in IEEE Security & Privacy, vol. 19, no. 3, pp. 42-49, May-June 2021.
  [ PDF ]

• Wenjie Xiong, André Schaller, Nikolaos A. Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser, and Jakub Szefer,
  "DRAM PUFs in Commodity Devices",
  in IEEE Design & Test, 2021.
  [ PDF ]

• Wenjie Xiong, Stefan Katzenbeisser, and Jakub Szefer,
  "Leaking Information Through Cache LRU States in Commercial Processors and Secure Caches",
  in IEEE Transactions on Computers (TC), vol. 70, no. 04, pp. 511-523, 2021.
  (Featured Paper in the April 2021 issue)
  [ PDF ]

• Wenjie Xiong, André Schaller, Stefan Katzenbeisser, and Jakub Szefer,
  "Software Protection using Dynamic PUFs",
  in IEEE Transactions on Information Forensics and Security (TIFS), May 2019.
  [ PDF ] 

• Shuwen Deng, Wenjie Xiong, and Jakub Szefer,
  "Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks"
  in Journal of Hardware and Systems Security (HASS), 2019
  [ PDF ] 

• Nikolaos Athanasios Anagnostopoulos, Tolga Arul, Yufan Fan, Christian Hatzfeld, André Schaller, Wenjie Xiong, Manishkumar Jain, Muhammad Umair Saleem, Jan Lotichius, Sebastian Gabmeyer, Jakub Szefer, and Stefan Katzenbeisser,
  "Intrinsic Run-Time Row Hammer PUFs: Leveraging the Row Hammer Effect for Run-Time Cryptography and Improved Security",
  in Cryptography, vol. 2, no. 3, June 2018.
  [ PDF ] 
  

• André Schaller^†, Wenjie Xiong^†, Nikolaos Athanasios Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Boris Skoric, Stefan Katzenbeisser and Jakub Szefer,
  "Decay-Based DRAM PUFs in Commodity Devices",
  in IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 16, issue 3, pp.462-475, May-June 1 2019.
  ^† The authors contributed equally.
  [ PDF ] 
  

Peer-reviewed Workshop Publications

• Hanieh Hashemi, Wenjie Xiong, Liu Ke, Kiwan Maeng, Murali Annavaram, G. Edward Suh, and Hsien-Hsin Lee,
  “Private Data Leakage via Exploiting Access Patterns of Sparse Features in Deep Learning-based Recommendation Systems”,
  Workshop on Trustworthy and Socially Responsible Machine Learning (TSRML), December 2022.
  [ PDF ][ arXiv ]

• Yongqin Wang, G. Edward Suh, Wenjie Xiong, Brian Knott, Benjamin Lefaudeux, Murali Annavaram, and Hsien-Hsin Lee,
  “Characterizing and Improving MPC-based Private Inference for Transformer-based Models”,
  NeurIPS 2021 Workshop on Privacy in Machine Learning, December 2021.
  [ PDF ]

• Shuwen Deng, Doğuhan Gümüşoğlu, Wenjie Xiong, Y. Serhan Gener, Onur Demir, and Jakub Szefer,
  "SecChisel Framework for Security Verification of Secure Processor Architectures",
  in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2019.
  [ PDF ] 
  

• Shuwen Deng, Wenjie Xiong, and Jakub Szefer,
  "Cache Timing Side-Channel Vulnerability Checking with Computation Tree Logic"
  in Proceedings of the Workshop on Hardware and Architectural Support for Security and Privacy (HASP), June 2018.
  [ PDF ] 
  

Technical Reports

• Onur Demir, Wenjie Xiong, Faisal Zaghloul, and Jakub Szefer,
  "Survey of Approaches for Security Verification of Hardware/Software Systems", August 2016.
  [ ePrint ]
  

News

• Wenjie Xiong, and Jakub Szefer,
  "Memristive fingerprints prove key destruction.", Nature Electronics 1(10), p.527, 2018.
  

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Teaching

• ECE5504/CS5504 Computer Architecture: 2022 Fall
• ECE2564 Embedded Systems: 2022 Spring

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Services

Conference/Workshop Organizing

• Publicity Chair for the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2023)
• Proceedings co-Chair for the 40th IEEE International Conference on Computer Design (ICCD 2022)
• Session Chair for session 1B: “Security I” in the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA-28)
• Session Chair for session 1: “the eternal war of side channels” in the IEEE International Symposium on Secure and Private Execution Environment Design (SEED 2021)
• Publications Chair for the IEEE International Symposium on Secure and Private Execution Environment Design (SEED 2021)
• Proceedings co-Chair for the 39th IEEE International Conference on Computer Design (ICCD 2021)
• Publicity Chair for the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2022)
• Organizing Committee of Secure and Private Systems for machine Learning (SPSL) workshop, co-located with ISCA 2021

Conferences/workshops Program Committees Activities

• ERC for the 50th International Symposium on Computer Architecture (ISCA)
• PC for 28th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'23)
• PC for Cryptographic Hardware and Embedded Systems (TCHES 2023)
• PC for International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2022)
• PC for the IEEE International Symposium on Secure and Private Execution Environment Design (SEED 2022)
• PC for Cryptographic Hardware and Embedded Systems (TCHES 2022)
• ERC for Architectural Support for Programming Languages and Operating Systems (ASPLOS 2022)
• PC for the 39th IEEE International Conference on Computer Design — Processor Architecture Track (ICCD 2021)
• ERC for Architectural Support for Programming Languages and Operating Systems (ASPLOS 2021)
• PC for the 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2020)
• PC for the 8th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2019)

Journal Reviewing Activities

• Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
• ACM Computing Surveys (CSUR)
• IEEE Computer Architecture Letters (CAL)
• Design Automation for Embedded Systems (DAEM)
• IEEE Security & Privacy
• IEEE Transactions on Circuits and Systems I
• IEEE Transactions on Computers (TC)
• Advanced Electronic Materials
• ACM Transactions on Architecture and Code Optimization (TACO)
• IEEE Design & Test
• Nature Electronics
• IEEE Access
• International Journal of Circuit Theory and Applications (CTA)
• IEEE Consumer Electronics Magazine
• ACM Transactions on Embedded Computing Systems (TECS)
• IEEE Transactions on Dependable and Secure Computing (TDSC)

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Openings

Getting involved! We are looking for postdocs, PhDs, Masters, and undergraduates to join us! Please email me. wenjiex@vt.edu