$whoami

I am a PhD candidate at Virginia Tech's Bradley Department of Electrical & Computer Engineering. My academic journey began with a Bachelor's degree in Electrical and Electronic Engineering from BUET, followed by a Master's degree from Auburn University. My primary focus lies in the security aspects of hardware and embedded systems, where I explore both potential vulnerabilities and the development of robust defenses. I am a member of the FoRTE-Research group (computer science), directed by Dr. Matthew Hicks, where I am engaged in the following three research strands:

Hardware-Oriented System Security: My interest in system-level security from a hardware perspective focuses on how physical and electrical phenomena such as device aging, process variation, timing behavior, and power consumption that can manifest into system-level vulnerabilities or create opportunities to leverage non-deterministic properties for security primitive design.

Cloud FPGA Security: Cloud service providers, such as AWS, offer CPU-FPGA virtual machines to accelerate compute-intensive workloads. However, the direct device-level access provided by FPGAs introduces numerous security implications. For instance, FPGAs can potentially act as power sensors for an entire server rack. I examine how an RTL-level access can significantly expands the attack surface in CPU-FPGA cloud environments.

Fake Chip Detection and Anti-Counterfeit Framework Design: The issue of counterfeit chips has become a severe problem, worsened by the ongoing global chip shortage due to factors such as the pandemic, geopolitical tensions, and natural disasters. To tackle this problem, I am developing robust schemes to detect and prevent counterfeit chips, aiming to enhance transparency and protect the integrity of the supply chain.

$man education

  1. Ph.D., Computer Engineering ('19-cont.), Virginia Tech
    Advisor: Dr. Matthew Hicks.
  2. M.S., Electrical & Computer Engineering'19, Auburn University
    Thesis: Towards Unclonable System Design for Resource-constrained Applications.
    Advisor: Dr. Ujjwal Guin.
  3. B.S., Electrical & Electronic Engineering'16, BUET
    Thesis: Metal-Insulator-Metal Ring Resonator for Sensing Applications.
    Advisor: Dr. Zahurul Islam.

$ls -lt publications

  1. Jubayer Mahmod and Matthew Hicks. UnTrustZone: Systematic Accelerated Aging to Expose On-chip Secrets. To appear: IEEE Security and Privacy (Oakland'24).
  2. Jubayer Mahmod and Matthew Hicks. SRAM Imprinting for System Protection and Differentiation. To appear: ACM ASIA Conference on Computer and Communications Security (AsiaCCS'24).
  3. Jubayer Mahmod and Matthew Hicks. Invisible Bits: Hiding Secret Messages in SRAM’s Analog Domain. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). March 2022.
  4. Jubayer Mahmod and Matthew Hicks. SRAM Has No Chill: Exploiting Power Domain Separation to Steal Onchip Secrets. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). March 2022.
  5. Jubayer Mahmod, and Ujjwal Guin. "A Robust, Low-Cost and Secure Authentication Scheme for IoT Applications." Cryptography 4.1 (2020): 8.
  6. Jubayer Mahmod, Millican Spencer, Ujjawal Guin, and Vishwani Agrawal. "Delay Fault Testing: Present and Future" Embedded tutorial, VTS 2019
  7. Benjamin Cyr, Jubayer Mahmod, Ujjwal Guin. "Low-Cost and Secure Firmware Obfuscation Method for Protecting Electronic Systems from Cloning" IEEE Internet of things Journal 2019.
  8. Jubayer Mahmod, Rakib Hyder, and Md Zahurul Islam. A Highly Sensitive Metal-Insulator-Metal Ring Resonator-Based Nanophotonic Structure for Biosensing Applications. "IEEE Sensors Journal (2018). [Note: undergraduate thesis]
  9. Jubayer Mahmod, Rakib Hyder, and Md Zahurul Islam. "Numerical studies on a plasmonic temperature nanosensor based on a metal-insulator-metal ring resonator structure for optical integrated circuit applications." Photonics and Nanostructures-Fundamentals and Applications 25 (2017): 52-57. [Note: undergraduate thesis]

Selected Projects

UnTrustZone

This project shows how long-term-data remanence is a threat to Trusted Execution System such as ARM TrustZone.

Voltboot

Creating artificial data retention in on-chip SRAM cell. This is a cold-style attack on on-chip SRAM, but without any cooling effect needed

Invisible Bits

This project is designed to conceal information in the analog layer of static random access memories (SRAM) with plausible deniability. The idea is to burn data into the transistor so that it is reflected in the SRAM's power-on state. The hidden information coexists with the data in the digital layer. That is, the system shows no signs of hidden data anywhere.


Cloud FPGA localization

Cloud service providers typically restrict access to low-level device information, such as device DNA. This project introduces an RTL design that utilizes the FPGA clock synthesizer to extract device behavior, enabling identification of specific FPGAs in the cloud. The system includes a hardware/software suite for seamless integration with AWS F1 instances, featuring necessary RTL and system service modules for signature extraction during the boot phase of the host CPU.

Reviewer

  1. Reviewer: IEEE Internet of Things Journal'22
  2. External reviewer (under the supervision of Dr. Guin and Dr. Hicks): IEEE Transactions on Circuits and Systems I'21 VLSID'19 DAC'19 GLSVLSI'19, Journal of Hardware and Systems Security'19 IEEE Transactions on Very Large Scale Integration Systems'17 &'18 VLSI Test Symposium'18 Transactions on Multi-Scale Computing Systems'18

Awards

  1. NSF Travel fellowship for ASPLOS'22
  2. International Symposium on Hardware Oriented Security and Trust (HOST) NSF travel grant.
  3. Graduate school tuition fellowship 2017-19 (MS in Auburn University).
  4. Best project award Tensilica Xtensa Embedded-DSP design contest 2016 (Organized by Cadence).
  5. Dean's list award and merit list award (BUET).

Technical Skills

Being in harwdare security research for 6+ years, I am exposed to pretty much all the layers in a system stack--- Silicon to Software. Here are some of the tools/systems/frameworks/architectures that I had opportunity to tinker with:
  1. Low level memory management (e.g., cache, TLB) and firmware security
  2. Coreboot and Linux kernel programming
  3. Intergated circuit aging and their security implications analysis
  4. Embedded system/flatforms and FPGA: Cortex-M, AVR, RPis, Xilinx FPGAs (7 series and Ultra scale+).
  5. Cadence Design suit and HSPICE for VLSI design.
  6. Hardware/software Co-design (e.g. ARM Cortex-A class to NIOS-II interface), ARM TrustZone, and Intel SGX
  7. Applied Cryptography
  8. I talk to the machines in C, python, Verilog, Assembly.