Synopsys Design Vision
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(New page: == What is Synopsys Design Vision == Synopsys Design Vision is a logic synthesis tool. It will take HDL designs and synthesize them to gate-level HDL netlists. It can synthesize to generic...) |
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Revision as of 18:09, 13 February 2008
What is Synopsys Design Vision
Synopsys Design Vision is a logic synthesis tool. It will take HDL designs and synthesize them to gate-level HDL netlists. It can synthesize to generic gates or to other design libraries such as the vtvt_tsmc libraries or OSU standard cell libraries. The tool exists in a gui and command line version. The gui version is referred to as design vision and the command line version is known as dc_shell-xg-t.
How to start Synopsys Design Vision
In the cvl or cesca cluster type the following commands to start the gui version:
Synopsys design_vision
To start the command shell of the tool instead type:
Synopsys dc_shell-xg-t
Basic Steps to Synthesizing Design
To
