ECE 5505 Extra Readings Home Page

The lectures also cover the following papers (not included in the textbooks) for each indicated topic in class.

Logic Simulation
1. "Accurate logic simulation in the presence of unknowns," (pdf)
  S. J. Chandra and J. H. Patel, Proc. International Conference on Computer-Aided Design, pp. 34-37, 1989.
2. "Restricted symbolic evaluation is fast and useful," (pdf)
  J. L. Carter, B. K. Rosen, G. L. Smith, and V. Pitchumani, Proc. International Conference on Computer-Aided Design, pp. 38-41, 1989.
3. "The inversion algorithm for digital simulation," (pdf)
  Maurer, P.M. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16 Issue 7 , July 1997 Page(s): 762 -769
Fault Modeling:
1. "Fast and accurate CMOS bridging fault simulation," (pdf)
  J. R. Rearick and J. H. Patel, Proc. International Test Conference, pp. 54-61, October 1993.
Fault Simulation
1. "PROOFS: A fast, memory-efficient sequential circuit fault simulator," (pdf)
  T. M. Niermann, W.-T. Cheng, and J. H. Patel, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11 no. 2 , Feb 1992 Page(s): 198-207
2. "Dynamic fault grouping for PROOFS: A win for large sequential circuits," (pdf)
  C. R. Graham, E. M. Rudnick, and J. H. Patel, Proc. International Conference on VLSI Design, pp. 495-501, January 1997.
3. "On potential fault detection in sequential circuits," (pdf)
  E. M. Rudnick, J. H. Patel, and I. Pomeranz, Proc. International Test Conference, pp. 142-149, October 1996.
4. "A fast, accurate, and non-statistical method for fault coverage estimation," (pdf)
  M. S. Hsiao, Proc. IEEE International Conference on Computer Aided Design, Nov. 1998, pp. 155-161
5. "On non-statistical techniques for fast fault coverage estimation,"
  M. S. Hsiao, Journal of Electronic Testing Theory and Applications, vol. 15, no. 3, pp. 239-254, December 1999.
Combinational ATPG
1. "Contest: a fast ATPG tool for very large combinational circuits," (pdf)
  Mahlstedt, U.; Gruning, T.; Ozcan, C.; Daehn, W. International Conf. Computer-Aided Design, 1990, pp. 222 -225.
2. "Test pattern generation using Boolean satisfiability," (pdf)
  Larrabee, T. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 11 no. 1 , Jan. 1992 pp. 4 -15.
Sequential ATPG
1. "Combinational test generation for various classes of acyclic sequential circuits" (pdf)
  Y. C. Kim, V. D. Agrawal, and K. K. Saluja, International Test Conference, 2001, pp. 1078-1087.
2. "Application of genetically-engineered finite-state-machine sequences to sequential circuit ATPG" (pdf)
  M. S. Hsiao, E. M. Rudnick, and J. H. Patel, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 239-254, March 1998
3. "Dynamic state traversal for sequential circuit test generation,"
  M. S. Hsiao, E. M. Rudnick, and J. H. Patel, ACM Transactions on Design Automation of Electronic Systems, vol. 5, no. 3, pp. 548-565, July, 2000.
Sequential Test Set Compaction
1. "Procedures for static compaction of test sequences for synchronous sequential circuits," (pdf)
  I. Pomeranz and S. M. Reddy, IEEE Trans. on Computers, vol. 49, no. 6, pp. 596-607, June 2000.
2. "Fast static compaction algorithms for sequential circuit test vectors," (pdf)
  M. S. Hsiao, E. M. Rudnick, and J. H. Patel, IEEE Trans. on Computers, vol. 48, no. 3, pp. 311-322, March 1999.
3. "Test set compaction using relaxed subsequence removal,"
  M. S. Hsiao and S. T. Chakradhar, Journal of Electronic Testing: Theory and Applications, vol. 16, no. 4, pp. 319-327, August, 2000.
4. "Test set and fault partitioning techniques for static test sequence compaction of sequential circuits,"
  M. S. Hsiao and S. T. Chakradhar, Journal of Electronic Testing Theory and Applications, vol. 16, no. 4, pp. 329-338, August, 2000.
5. "Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration," (pdf)
  R. Guo, I. Pomeranz, and S. M. Reddy, Proc. IEEE Design, Automation and Test in Europe, 1998, pp. 583 -587.
6. "PROPTEST: a property based test pattern generator for sequential circuits using test compaction," (pdf)
  R. Guo, S. M. Reddy, and I. Pomeranz, Proc. IEEE Design Automation Conference, 1999, pp. 653 -659.
7. "Efficient spectral techniques for sequential ATPG," (pdf)
  A. Giani, S. Sheng, M. S. Hsiao, and V. D. Agrawal, Proceedings of the IEEE Design Automation and Test in Europe Conference, March, 2001, pp. 204-208.
Redundancy:
1. "FIRE: a fault-independent combinational redundancy identification algorithm," (pdf)
  M. A. Iyer and M. Abramovici, IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 4 no. 2 , June 1996, pp. 295 -301
2. "Static logic implication with application to redundancy identification," (pdf)
  J.-K. Zhao, E. M. Rudnick, and J. H. Patel, Proc. VLSI Test Symposium, pp. 288-293, April 1997.
3. "A graph traversal based framework for sequential logic implication with an application to c-cycle redundancy identification," (pdf)
  J.-K. Zhao, J. A. Newquist, and J. H. Patel, Proc. VLSI Design Conf., pp. 163-169, 2001.
4. "Combinational ATPG theorems for identifying untestable faults in sequential circuits," (pdf)
  V. D. Agrawal and S. T. Chakradhar, IEEE Trans. Computer-Aided Design, vol. 14, no. 9, Sept. 1995, pp. 1155-1160
5. "MUST: multiple-stem analysis for identifying sequentially untestable faults," (pdf)
  Q. Peng; M. Abramovici, J. Savir, Proc. Intl Test Conference, 2000. pp. 839 -846
Delay Testing
1. "Classification and identification of nonrobust untestable path delay faults," K.-T. Cheng and H.-C. Chen, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 8, pp. 845-854, August 1996.
2. "Delay-verifiability of combinational circuits based on primitive faults," W. Ke and P. R. Menon, International Conf. Computer Aided Design, pp. 86-90, 1994.
3. "Fast identification of untestable delay faults using implications," K. Heragu, J. H. Patel, and V. D. Agrawal, International Conf. Computer Aided Design, pp. 642-647, 1997.
4. "An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits," I. Pomeranz and S. M. Reddy, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 2, pp. 240-250, Feb. 1994.
DFT:
1. "Sequential circuit testability enhancement using a nonscan approach," (pdf)
  E. M. Rudnick, V. Chickermane, P. Banerjee, and J. H. Patel, IEEE Trans. VLSI Systems, vol. 3, no. 2, pp. 333-338, June 1995.
2. "A global algorithm for the partial scan design problem using circuit state information," (pdf)
  D. Xiang and J. H. Patel, Proc. International Test Conference, pp. 548-556, October 1996.
3. "Partial scan beyond cycle cutting," (pdf)
  G. S. Saund, M. S. Hsiao, and J. H. Patel, Proc. Fault Tolerant Computing Symposium, Jun., 1997, pp. 320-328.
4. "Partial scan selection based on dynamic reachability and observability information," (pdf)
  M. S. Hsiao, G. S. Saund, E. M. Rudnick, and J. H. Patel, Proc. International Conference on VLSI Design, January 1998, pp. 174-180.
5. "Partial scan using multi-hop state reachability analysis," (pdf)
  S. Sharma and M. S. Hsiao, Proc. IEEE VLSI Test Symposium, April, 1999, pp. 121-126.
6. "Enhancing high-level control-flow for improved testability," (pdf)
  F. Hsu, E. M. Rudnick, and J. H. Patel, Proc. International Conf. Computer-Aided Design, 1996, pp. 322-328.
Diagnosis:
1. "Fault equivalence identification using redundancy information and static and dynamic extraction," (pdf)
  Amyeen, M.E.; Fuchs, W.K.; Pomeranz, I.; Boppana, V. Proc. VLSI Test Symposium, 2001 pp. 124 -130

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