Synopsys Tutorial: Power Estimation

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By Syed Haider
 
By Syed Haider
  
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== Note ==
  
== Setting Up Standard Cell Library and Project Directory ==
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We had a tutorial on how to use PrimeTime Power Estimation here, but we were informed that this might violate the EULA as provided by Synopsys for the University Program.
1. Download Oklahoma State University Library from http://vcag.ecen.okstate.edu/projects/scells/
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Specifically, from: http://vcag.ecen.okstate.edu/projects/scells/download/iit_stdcells_v2.3beta/
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If you would like to see this tutorial, please contact support@ece.vt.edu
 
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Download  the iitcells_lib_2.3.tar.gz package.
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2. untar the library somewhere nice like your home directory where you will really never touch it (i.e. /home/syedh/). The Directory will be called iit_stdcells.
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3. Create a project directory somewhere else. (example: mkdir /home/syedh/Project1)
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In Project1 create another directory called WORK.
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4. Back in Project1 directory create an empty file called: '''.synopsys_dc.setup'''
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This file will specify to Synopsys and design_vision software what libraries you are using. A sample version of the file is listed below. The path after “/home/syedh/” should remain unchanged if this tutorial is being followed correctly!!!
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# .synopsys_dc.setup file
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# Define the target tehcnology library, symbol library,
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# and link libraries
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set target_library /home/syedh/iit_stdcells/lib/tsmc018/lib/iit018_stdcells.db
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#do not have a symbol library
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#set symbol_library
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#set link library (set as same as target library)
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set link_library “/home/syedh/iit_stdcells/lib/tsmc018/lib/iit018_stdcells.db *”
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set designer "Your Name"
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5. Copy /home/syedh/iit_stdcells/lib/tsmc018/lib/iit018_stdcells.v into Project1 Directory.
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6. Now it is design time. Create verilog description of something amazing. Here is a design of a full adder and some registers that spans multiple design files (full_adder.v, top.v):
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//full_adder.v
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//This is a module for a 1 bit Full Adder
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module full_adder(a,b, c_in, s, c_out);
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input a, b, c_in;
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output wire s, c_out;
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assign s = a ^ b ^ c_in;
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assign c_out = ((a & b)) | (c_in & (a^b));
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endmodule
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//top.v
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//This contains a full adder with some registers for input and output.
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`timescale 1ns/10ps
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module top (clk, a, b, c_in, sum, c_out);
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input clk, a, b, c_in;
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output sum, c_out;
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reg in_a;
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reg in_b;
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reg sum_reg;
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reg c_out_reg;
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reg c_in_reg;
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full_adder fa1(.a(in_a), .b(in_b), .c_in(c_in_reg), .s(sum), .c_out(c_out));
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always @(posedge clk)
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begin
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in_a = a;
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in_b = b;
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c_in_reg = c_in;
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c_out_reg = c_out;
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sum_reg = sum;
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end
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endmodule
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7. Now it is time to create a test bench file to test the design. The things that will be highlighted in purple are system tasks that will create dumps (value change dumps) of signals in your design.
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//tb_top.v
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//testbench
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`timescale 1ns/10ps
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module tb_top();
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reg clk;
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reg a, b, c_in;
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wire c_out, sum;
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//clocking description
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initial
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begin
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clk = 0;
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end
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//clock period is #100
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always begin
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#50
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clk = ~clk;
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end
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//initialize input to full adder
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initial begin
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a = 0;
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b = 0;
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c_in = 0;
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end
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///////////////////////////////
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// Toggle the inputs at varying rates
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///////////////////////////////
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//toggle carry_in
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initial begin
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#60;
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repeat (50)
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begin
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c_in <= ~c_in;
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#100;
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end
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end
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//toggle a
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initial begin
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#60;
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repeat (25)
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begin
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a <= ~a;
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#200;
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end
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end
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//toggle b and setup vcd dump
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initial begin
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$dumpfile("dmp_top.vcd"); //read verilog book for more info on system command
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$dumpvars(0,top);
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#60;
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$dumpon;
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repeat (10)
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begin
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b <= ~b;
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#500;
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end
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$dumpoff;
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$finish;  //ends simulation
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end
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//Module under test
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top uut(.clk(clk), .a(a), .b(b), .c_in(c_in), .sum(sum), .c_out(c_out));
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endmodule
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8. Now comes the time to create a synthesized top level design from {full_adder.v top.v}. We are interested in creating a synthesized version of “top”. At command prompt type the following:
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Synopsys
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design_vision
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Now a design_vision gui has started up. In this gui follow these steps:
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In Menu: File --> Analyze.
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A Dialog box will appear called “Analyze Designs”. Click the “Add..” button and add every design file {full_adder.v top.v}. You can do this one file at a time or all at one time by using the CTRL key to select multiple files. After adding all the files press OK.
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In Menu: Design --> Elaborate.
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A Dialog box will appear called “Elaborate Designs”. There will be a drop down selection menu called “Design”. In this selection menu there will be two objects listed: top(verilog) and full_adder(verilog). Make sure that top(verilog) is selected. Press OK.
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Now in the Design Vision the “Hier 1” window will have objects listed in it.
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In Menu: Design --> Compile. In the dialog box that shows up press OK.
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In Menu: File --> Save As.  Save the design as a verilog design with a new name (ex. top_syn.v).
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9. Exit the gui and in the command prompt type exit to quit out of the design_vision_xg_t shell. Then type exit again to quit Synopsys.
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10. Now it is time to simulate the synthesized design, top_syn.v, with the testbench, tb_top.v. The verilog simulator program of Synopsys is called VCX. The first step is to write a script for the simulation:
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#vcs_script.scr
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#This is a script file for VCX simulator
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./tb_top.v
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./top_syn.v
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-v ./iit018_stdcells.v
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+libext+.v +nolibcell +define+VPD+SAIF+VCD+SDF
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11. At command prompt type: Synopsys
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      Now type: vcs -f vcs_script.scr
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      The result of running this command is that an executable called simv is created.
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12. Run simv : ./simv
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13. Now the file dmp_top.vcd has been created.
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14. Now we will use a tool called PrimeTime-Px to get power estimation. The following script called power.scr will be used.
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#power.scr
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set power_enable_analysis TRUE
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set target_library "/home/syedh/iit_stdcells/lib/tsmc018/lib/iit018_stdcells.db"
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set link_library "/home/syedh/iit_stdcells/lib/tsmc018/lib/iit018_stdcells.db *"
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read_db $target_library
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read_verilog top_syn.v
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current_design test_inverter
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link
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read_vcd dmp_top.vcd -strip_path tb_top/uut
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create_power_waveforms –output vcd
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report_power
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15. At the Synopsys command prompt type: pt_shell
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      Now run the power.scr: source power.scr
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16. If all went right the output from the script should look something like this:
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======================================================================
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Summary:
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Total number of nets = 11
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Number of annotated nets = 11 (100.00%)
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Total number of leaf cells = 7
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Number of fully annotated leaf cells = 7 (100.00%)
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======================================================================
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Information: The waveform options are:
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                File name:      power_waves.fsdb
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                File format:    fsdb
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                Time interval:  0.01ns
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                Hierarchical level:    all
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Information: Power analysis is running, please wait ...
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Information: analysis is done for time window (0ns - 5050ns)
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****************************************
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Report : Event Based Power
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Design : top
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Version: Z-2007.06-SP3
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Date  : Wed Feb 13 14:34:11 2008
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****************************************
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  Attributes
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  ----------
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      i  -  Including register clock pin internal power
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      u  -  User defined power group
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                        Internal  Switching  Leakage    Total
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Power Group            Power    Power      Power      Power  (    %)  Attrs
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--------------------------------------------------------------------------------
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io_pad                    0.0000    0.0000    0.0000    0.0000 ( 0.00%)
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memory                    0.0000    0.0000    0.0000    0.0000 ( 0.00%)
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black_box                  0.0000    0.0000    0.0000    0.0000 ( 0.00%)
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clock_network          3.292e-06    0.0000    0.0000 3.292e-06 (58.67%)  i
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register                6.722e-07 4.735e-07 4.822e-10 1.146e-06 (20.42%)
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combinational          8.640e-07 3.086e-07 4.037e-10 1.173e-06 (20.90%)
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sequential                0.0000    0.0000    0.0000    0.0000 ( 0.00%)
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  Net Switching Power  = 7.821e-07  (13.94%)
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  Cell Internal Power  = 4.828e-06  (86.05%)
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  Cell Leakage Power  = 8.859e-10  ( 0.02%)
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                        ---------
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Total Power            = 5.611e-06  (100.00%)
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X Transition Power    =    0.0000
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Glitching Power        = 2.152e-08
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Peak Power            = 4.726e-03
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Peak Time              =  550.100
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Latest revision as of 13:49, 18 June 2015

Power Estimation with OSU Standard Cell Library and Synopsys tools (PrimeTime-Px)

By Syed Haider

[edit] Note

We had a tutorial on how to use PrimeTime Power Estimation here, but we were informed that this might violate the EULA as provided by Synopsys for the University Program.

If you would like to see this tutorial, please contact support@ece.vt.edu

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