Welcome To The ECE 4520/5505 Project Home Page

All programs are to be written in C or C++. All programs are to be compilable and executable in the Unix/Solaris or Linux environment.

Here are the project grades .

1. Project 0: Warm-up project (due Sept 11)
2. Project 1: Reconvergent Fanouts (due Sept 23)
3. Project 2: 3-value Logic Simulation with FF signal probability (due Oct 9)
4. Final Project for graduate students: (report & presentation required) (due Dec. 11)
   proposal due Oct. 22
   Possible Topics:
   
   • PODEM for sequential circuits (9-values needed)
   • Untestable fault identification using implications
   • ATPG-based equivalence checking
   • Path delay fault ATPG
   • Path delay fault simulation
   • False path identification
   • Fault diagnosis
   • Spectral characterization of the logic circuit
   • Enhanced combinational test pattern generation using advanced techniques
   • Test set compaction
   • Non-trivial (functional but not structural) equivalent fault identification
   • Simulation-based test pattern generation
     • Logic-simulation-based ATPG, and/or
     • Fault-simulation-based ATPG
   • Hardware Fault Simulation Engine using FPGA
   • Bridging Fault Simulation and/or Vec Generation
   • Transition Fault Simulation and/or Vec Generation
   • Path-delay Fault Simulation and/or Vec Generation
   • Software testing by first converting software into a hardware representation
   • others (feel free to discuss with me any ideas you may have, such as variations to the suggested above or those not listed here)

Additional comb. ckts
Additional seq. ckts