Electronic Design Automation Supplemental Readings Home Page

The lectures also cover the following papers, which you may download from the publishers (e.g., ieeexplore) or by simply searching the internet.

Please also note that more papers may be added to this list over time.

    Espresso

  1. "Multiple-Valued Minimization for PLA Optimization," Rudell, R.L.; Sangiovanni-Vincentelli, A.; in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Volume: 6 Issue:5, September 1987, On page(s): 727 - 750

    BDDs

  2. "Efficient implementation of a BDD package," Brace, K.S.; Rudell, R.L.; Bryant, R.E. Proc. Design Automation Conference, 1990. Page(s): 40 -45
  3. "Efficient variable ordering heuristics for shared ROBDD," Chung, P.-Y.; Hajj, I.M.; Patel, J.H. Proc. Intl Symp. Circuits and Systems, 1993., Page(s): 1690 -1693 vol.3
  4. "Symmetry Detection And Dynamic Variable," Panda, S.; Somenzi, F.; Plessier, B.F. Proc. Intl Conf. Computer-Aided Design, 1994., Page(s): 628 -631
  5. "Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions," A. Narayan, J. Jain, M. Fujita, A. Sangiovanni-Vincentelli, Proc. Intl Conf. Computer-Aided Design, 1996. Page(s): 547 -554

    Algebraic Factorization

  6. "The decomposition and factorization of Boolean expresions," R. K. Brayton and C. McMullen, Proc. IEEE Int. Symp. Circuits and Systems, May 1982, pp. 49-54.
  7. "Boolean division and factorization using binary decision diagrams," T. Stanion, C. Sechen, IEEE. Trans. CAD, vol. 13, no. 9, pp. 1179-1184, Sep 1994.

    Technology Mapping

  8. "DAGON: Technology binding and local optimization by DAG matching," K. Keutzer, Proc. IEEE Design Automation Conf., 1987, pp. 341-347.

    Partitioning

  9. “An efficient heuristic procedure for partitioning graphs,” (pdf) W. Kernighan and S. Lin, Bell System Technical Journal, 1970.
  10. “A linear-time heuristics for improving network partitions,” C.M. Fiduccia and R.M. Mattheyses, in Proc. Design Automation Conference (DAC), pp.175-181, 1982.
  11. “Optimization by simulated annealing”, S. Kirkpatrick, C.D. Gelatt Jr., M.P. Vecchi, Science, vol.220, no.4598, pp.671-680, 1983.

    Floorplanning

  12. “Constrained floorplan design for flexible blocks,” S-K. Dong, J. Cong, and C.L. Liu, in Proc. ICCAD, pp.488-491, 1989.

    Placement and Routing

  13. “A Procedure for Placement of Standard-Cell VLSI Circuits”, A.E. Dunlop and B.W. Kernighan, IEEE Trans. TCAD, vol.4, no.1, pp.92-98, January, 1985.
  14. “The Timberwolf Placement and Routing Package,” C. Sechen and A. Sangiovanni-Vincentelli, IEEE Journal Solid-State Circuits, vol. SC-20, no. 2, pp. 510-522, 1985.
  15. “Timber wolf 3.2: A New Standard Cell Placement and Global Routing Package,” C. Sechen and A. Sangiovanni-Vincentelli, in Proc. DAC, pp.432-439, 1986.
  16. “An Algorithm for Path Connection and its Application,” C.Y. Lee, IRE Transactions on Electronic Computers, 1961.
  17. “Wire Routing by Optimizing Channel Assignment within Large Apertures”, A. Hashimoto and J. Stevens, in Proc. DAC, pp. 155-169, 1971.
  18. “A dogleg channel router,” D.N. Deutch, in Proc. DAC, pp.425-433, 1976.
  19. “Efficient Algorithms for Channel Routing,” T. Yoshimura and E. Kuh, in IEEE Trans. Computer-Aided Design, vol.CAD-1, pp.25-35, January, 1982.
  20. “Stochastic evolution: A fast effective heuristic for some generic layout problems”, Y. Saab and V. Rao, in Proc. Design Automation Conf. (DAC), pp.26-31, 1990

    High-Level Scheduling

  21. “Parallel sequencing and assembly line problems,” T.C. Hu, Operations Research, no.9, pp.841-848, 1961.
  22. “Force-directed scheduling for the behavioral synthesis of ASIC’s,” P. Paulin and J. Knight, in IEEE Trans. Computer-Aided Design, vol. 8, no. 6, pp. 661-679, July, 1989.