Verification of Digital Systems
Tentative Course Schedule


No. Topic Lecture Notes Reading
  INTRODUCTION   
1 Course Outline & Introduction lec01.pdf Ch. 1
2 Review of Graph Algorithms & Complexity lec02.pdf Ch. 3
  COMBINATIONAL CIRCUIT VERIFICATION    
3 Containment Check lec03.pdf Ch. 5.2
4 SAT-based Equivalence Checking lec04.pdf Extra Reading
5 Learning-based Equivalence Checking lec05.pdf Extra Reading
6 BDD-based Equivalence Checking lec06.pdf Ch. 6
7 BDD-based Equivalence Checking II lec07.pdf Ch. 6
8 BDD-based Equivalence Checking III lec08.pdf Extra Reading
9 Incremental Multi-Level Combinational Verification lec09.pdf Extra Reading
10 More Multi-Level Combinational Verification lec10.pdf Extra Reading
  SEQUENTIAL CIRCUIT VERIFICATION  
11 Sequential Logic Verification lec11.pdf Ch. 7.1 - 7.7
12 Sequential Logic Verification Using BDDs lec12.pdf Ch. 7.8 - 7.11
13 Incremental Sequential Verification lec13.pdf Extra Reading
14 Advanced Sequential Verification lec14.pdf Extra Reading
15 RTL To Gate Verification lec15.pdf Extra Reading
  PROPERTY-BASED VERIFICATION  
16 Computational Tree Logic & MC Formulation lec16.pdf Extra Reading
17 Unbounded Symbolic Model Checking lec17.pdf Extra Reading
18 More Model Checking (Unbounded and Bounded) lec18.pdf Extra Reading
  SIMULATION-BASED VERIFICATION  
19 Error-Directed Simulation + Symbolic Simulation lec19.pdf Extra Reading
20 Coverage-Directed Simulation Based Verification lec20.pdf Extra Reading
21 Coverage-Directed Simulation Based Verification II lec21.pdf Extra Reading
22 Architectural Level Verification lec22.pdf Extra Reading
  DESIGN ERROR DIAGNOSIS  
23 Diagnosis I lec23.pdf Extra Reading
24 Diagnosis II lec24.pdf Extra Reading
  EXAMS & PROJECT PRESENTATIONS  
25 Exam I    
26 Project Presentations    
27 Exam II    
Note 1: Some lectures take more than one class session
Note 2: Lectures cover extra readings

Homework Assignments
Projects


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