# 9 inputs
# 11 outputs
# 15 D-type flipflops
# 59 inverters
# 101 gates (44 ANDs + 18 NANDs + 9 ORs + 30 NORs 0 XORs 0 XNORs)

INPUT(START)
INPUT(B0)
INPUT(B1)
INPUT(B2)
INPUT(B3)
INPUT(A0)
INPUT(A1)
INPUT(A2)
INPUT(A3)

OUTPUT(P4)
OUTPUT(P5)
OUTPUT(P6)
OUTPUT(P7)
OUTPUT(P0)
OUTPUT(P1)
OUTPUT(P2)
OUTPUT(P3)
OUTPUT(CNTVCON2)
OUTPUT(CNTVCO2)
OUTPUT(READY)

CT2 = DFF(CNTVG3VD)
CT1 = DFF(CNTVG2VD)
CT0 = DFF(CNTVG1VD)
ACVQN3 = DFF(ACVG4VD1)
ACVQN2 = DFF(ACVG3VD1)
ACVQN1 = DFF(ACVG2VD1)
ACVQN0 = DFF(ACVG1VD1)
MRVQN3 = DFF(MRVG4VD)
MRVQN2 = DFF(MRVG3VD)
MRVQN1 = DFF(MRVG2VD)
MRVQN0 = DFF(MRVG1VD)
AX3 = DFF(AM3)
AX2 = DFF(AM2)
AX1 = DFF(AM1)
AX0 = DFF(AM0)

P4 = NOT(ACVQN0)
CNTVG3VQN = NOT(CT2)
ACVPCN = NOT(START)
CT1N = NOT(CT1)
CNTVG2VQN = NOT(CT1)
CNTVCON0 = NOT(CT0)
CNTVG1VQN = NOT(CT0)
P6 = NOT(ACVQN2)
P5 = NOT(ACVQN1)
P0 = NOT(MRVQN0)
P2 = NOT(MRVQN2)
P7 = NOT(ACVQN3)
P3 = NOT(MRVQN3)
P1 = NOT(MRVQN1)
AMVS0N = NOT(INIT)
CNTVCO0 = NOT(CNTVG1VQN)
READY = NOT(READYN)
BMVS0N = NOT(READYN)
AMVG5VS0P = NOT(AMVS0N)
AMVG4VS0P = NOT(AMVS0N)
AMVG3VS0P = NOT(AMVS0N)
AMVG2VS0P = NOT(AMVS0N)
AD0 = NOT(AD0N)
AD1 = NOT(AD1N)
AD2 = NOT(AD2N)
AD3 = NOT(AD3N)
CNTVG1VD1 = NOT(READY)
BMVG5VS0P = NOT(BMVS0N)
BMVG4VS0P = NOT(BMVS0N)
BMVG3VS0P = NOT(BMVS0N)
BMVG2VS0P = NOT(BMVS0N)
CNTVG3VD1 = NOT(CNTVCON1)
SMVS0N = NOT(ADSH)
MRVSHLDN = NOT(ADSH)
ADDVC1 = NOT(ADDVG1VCN)
SMVG5VS0P = NOT(SMVS0N)
SMVG4VS0P = NOT(SMVS0N)
SMVG3VS0P = NOT(SMVS0N)
SMVG2VS0P = NOT(SMVS0N)
CNTVG1VZ = NOT(CNTVG1VZ1)
AM3 = NOT(AMVG5VX)
AM2 = NOT(AMVG4VX)
AM1 = NOT(AMVG3VX)
AM0 = NOT(AMVG2VX)
S0 = NOT(ADDVG1VP)
BM3 = NOT(BMVG5VX)
BM2 = NOT(BMVG4VX)
BM1 = NOT(BMVG3VX)
BM0 = NOT(BMVG2VX)
ADDVC2 = NOT(ADDVG2VCN)
S1 = NOT(ADDVG2VSN)
ADDVC3 = NOT(ADDVG3VCN)
S2 = NOT(ADDVG3VSN)
SM0 = NOT(SMVG2VX)
CO = NOT(ADDVG4VCN)
S3 = NOT(ADDVG4VSN)
SM1 = NOT(SMVG3VX)
SM3 = NOT(SMVG5VX)
SM2 = NOT(SMVG4VX)

AMVG5VG1VAD1NF = AND(AMVS0N, AX3)
AMVG4VG1VAD1NF = AND(AMVS0N, AX2)
AMVG3VG1VAD1NF = AND(AMVS0N, AX1)
AMVG2VG1VAD1NF = AND(AMVS0N, AX0)
BMVG5VG1VAD1NF = AND(BMVS0N, P3)
BMVG4VG1VAD1NF = AND(BMVS0N, P2)
BMVG3VG1VAD1NF = AND(BMVS0N, P1)
BMVG2VG1VAD1NF = AND(BMVS0N, P0)
AMVG5VG1VAD2NF = AND(AMVG5VS0P, A3)
AMVG4VG1VAD2NF = AND(AMVG4VS0P, A2)
AMVG3VG1VAD2NF = AND(AMVG3VS0P, A1)
AMVG2VG1VAD2NF = AND(AMVG2VS0P, A0)
ADDVG2VCNVAD1NF = AND(AD1, P5)
ADDVG3VCNVAD1NF = AND(AD2, P6)
ADDVG4VCNVAD1NF = AND(AD3, P7)
MRVG3VDVAD1NF = AND(ADSH, P3)
MRVG2VDVAD1NF = AND(ADSH, P2)
MRVG1VDVAD1NF = AND(ADSH, P1)
BMVG5VG1VAD2NF = AND(BMVG5VS0P, B3)
BMVG4VG1VAD2NF = AND(BMVG4VS0P, B2)
BMVG3VG1VAD2NF = AND(BMVG3VS0P, B1)
BMVG2VG1VAD2NF = AND(BMVG2VS0P, B0)
SMVG5VG1VAD1NF = AND(SMVS0N, P7)
SMVG4VG1VAD1NF = AND(SMVS0N, P6)
SMVG3VG1VAD1NF = AND(SMVS0N, P5)
SMVG2VG1VAD1NF = AND(SMVS0N, P4)
ADDVG2VCNVAD4NF = AND(ADDVC1, AD1, P5)
ADDVG2VCNVAD2NF = AND(ADDVC1, ADDVG2VCNVOR1NF)
MRVG4VDVAD1NF = AND(ADSH, S0)
MRVG4VDVAD2NF = AND(MRVSHLDN, BM3)
MRVG3VDVAD2NF = AND(MRVSHLDN, BM2)
MRVG2VDVAD2NF = AND(MRVSHLDN, BM1)
MRVG1VDVAD2NF = AND(MRVSHLDN, BM0)
ADDVG2VCNVAD3NF = AND(ADDVG2VCNVOR2NF, ADDVG2VCN)
ADDVG3VCNVAD4NF = AND(ADDVC2, AD2, P6)
ADDVG3VCNVAD2NF = AND(ADDVC2, ADDVG3VCNVOR1NF)
ADDVG3VCNVAD3NF = AND(ADDVG3VCNVOR2NF, ADDVG3VCN)
SMVG2VG1VAD2NF = AND(SMVG2VS0P, S1)
ADDVG4VCNVAD4NF = AND(ADDVC3, AD3, P7)
ADDVG4VCNVAD2NF = AND(ADDVC3, ADDVG4VCNVOR1NF)
ADDVG4VCNVAD3NF = AND(ADDVG4VCNVOR2NF, ADDVG4VCN)
SMVG3VG1VAD2NF = AND(SMVG3VS0P, S2)
SMVG5VG1VAD2NF = AND(SMVG5VS0P, CO)
SMVG4VG1VAD2NF = AND(SMVG4VS0P, S3)

ADDVG1VPVOR1NF = OR(AD0, P4)
ADDVG2VCNVOR1NF = OR(AD1, P5)
ADDVG3VCNVOR1NF = OR(AD2, P6)
ADDVG4VCNVOR1NF = OR(AD3, P7)
CNTVG2VG2VOR1NF = OR(CT1, CNTVG2VD1)
CNTVG3VG2VOR1NF = OR(CT2, CNTVG3VD1)
ADDVG2VCNVOR2NF = OR(ADDVC1, AD1, P5)
ADDVG3VCNVOR2NF = OR(ADDVC2, AD2, P6)
ADDVG4VCNVOR2NF = OR(ADDVC3, AD3, P7)

READYN = NAND(CT0, CT1N, CT2)
AD0N = NAND(P0, AX0)
AD1N = NAND(P0, AX1)
AD2N = NAND(P0, AX2)
AD3N = NAND(P0, AX3)
CNTVCON2 = NAND(CT2, CNTVCO1)
CNTVCON1 = NAND(CT1, CNTVCO0)
ADDVG1VCN = NAND(AD0, P4)
CNTVG2VZ1 = NAND(CT1, CNTVG2VD1)
CNTVG1VZ1 = NAND(CT0, CNTVG1VD1)
CNTVG3VZ1 = NAND(CT2, CNTVG3VD1)
ADDVG1VP = NAND(ADDVG1VPVOR1NF, ADDVG1VCN)
CNTVG2VZ = NAND(CNTVG2VG2VOR1NF, CNTVG2VZ1)
CNTVG3VZ = NAND(CNTVG3VG2VOR1NF, CNTVG3VZ1)
ACVG1VD1 = NAND(ACVPCN, SM0)
ACVG2VD1 = NAND(ACVPCN, SM1)
ACVG4VD1 = NAND(ACVPCN, SM3)
ACVG3VD1 = NAND(ACVPCN, SM2)

INIT = NOR(CT0, CT1, CT2)
CNTVCO1 = NOR(CNTVG2VQN, CNTVCON0)
ADSH = NOR(READY, INIT)
CNTVG2VD1 = NOR(READY, CNTVCON0)
CNTVCO2 = NOR(CNTVG3VQN, CNTVCON1)
AMVG5VX = NOR(AMVG5VG1VAD2NF, AMVG5VG1VAD1NF)
AMVG4VX = NOR(AMVG4VG1VAD2NF, AMVG4VG1VAD1NF)
AMVG3VX = NOR(AMVG3VG1VAD2NF, AMVG3VG1VAD1NF)
AMVG2VX = NOR(AMVG2VG1VAD2NF, AMVG2VG1VAD1NF)
BMVG5VX = NOR(BMVG5VG1VAD2NF, BMVG5VG1VAD1NF)
BMVG4VX = NOR(BMVG4VG1VAD2NF, BMVG4VG1VAD1NF)
BMVG3VX = NOR(BMVG3VG1VAD2NF, BMVG3VG1VAD1NF)
BMVG2VX = NOR(BMVG2VG1VAD2NF, BMVG2VG1VAD1NF)
CNTVG2VD = NOR(CNTVG2VZ, START)
CNTVG1VD = NOR(CNTVG1VZ, START)
CNTVG3VD = NOR(CNTVG3VZ, START)
ADDVG2VCN = NOR(ADDVG2VCNVAD2NF, ADDVG2VCNVAD1NF)
MRVG4VD = NOR(MRVG4VDVAD2NF, MRVG4VDVAD1NF)
MRVG3VD = NOR(MRVG3VDVAD2NF, MRVG3VDVAD1NF)
MRVG2VD = NOR(MRVG2VDVAD2NF, MRVG2VDVAD1NF)
MRVG1VD = NOR(MRVG1VDVAD2NF, MRVG1VDVAD1NF)
ADDVG2VSN = NOR(ADDVG2VCNVAD4NF, ADDVG2VCNVAD3NF)
ADDVG3VCN = NOR(ADDVG3VCNVAD2NF, ADDVG3VCNVAD1NF)
ADDVG3VSN = NOR(ADDVG3VCNVAD4NF, ADDVG3VCNVAD3NF)
SMVG2VX = NOR(SMVG2VG1VAD2NF, SMVG2VG1VAD1NF)
ADDVG4VCN = NOR(ADDVG4VCNVAD2NF, ADDVG4VCNVAD1NF)
ADDVG4VSN = NOR(ADDVG4VCNVAD4NF, ADDVG4VCNVAD3NF)
SMVG3VX = NOR(SMVG3VG1VAD2NF, SMVG3VG1VAD1NF)
SMVG5VX = NOR(SMVG5VG1VAD2NF, SMVG5VG1VAD1NF)
SMVG4VX = NOR(SMVG4VG1VAD2NF, SMVG4VG1VAD1NF)