-------------------------------------------------------------------------------- -- Differential Equation Benchmark -------------------------------------------------------------------------------- PACKAGE diffeq_types IS SUBTYPE nat is integer; END diffeq_types; USE work.diffeq_types.all; entity diffeq is port (Xinport: in nat; Yinport: in nat; Uinport: in nat; Aport : in nat; DXport : in nat; Xoutport: out nat; Youtport: out nat; Uoutport: out nat; CLK : in bit); end diffeq; --============================================================ architecture diffeq of diffeq is signal oldx, oldy, oldu : nat; signal newx, newy, newu : nat; begin --============================================================ MAIN : process (CLK, Aport, DXport, Xinport, Yinport, Uinport) variable x_var, y_var, u_var, a_var, dx_var: nat; variable y1, t1,t2,t3,t4,t5,t6: nat; variable looping : bit; begin if (CLK'event and CLK = '1') then if (looping = '0') then x_var := Xinport; y_var := Yinport; u_var := Uinport; looping := '1'; else x_var := newx; y_var := newy; u_var := newu; end if; a_var := Aport; dx_var := DXport; if (x_var < a_var) then t1 := u_var * dx_var; t2 := 3 * x_var; t3 := 3 * y_var; t4 := t1 * t2; t5 := dx_var * t3; t6 := u_var - t4; u_var := t6 - t5; y1 := u_var * dx_var; y_var := y_var + y1; x_var := x_var + dx_var; oldx <= x_var; oldy <= y_var; oldu <= u_var; else Xoutport <= x_var; Youtport <= y_var; Uoutport <= u_var; looping := '0'; end if; end if; end process; --============================================================ SYNCH: process(CLK, oldx, oldy, oldu) begin if (CLK'event and CLK = '1') then newx <= oldx; newy <= oldy; newu <= oldu; end if; end process; --============================================================ end diffeq;